This application relates to data communications, and more particularly to communication of signals between different clock domains.
The increasing complexity of electronic products now often requires a single system, or even a single integrated circuit chip, to have multiple asynchronous clocks and/or clocks with very different clock frequencies. As but one example, it is common for the input/output interfaces that communicate with external devices to be inherently asynchronous from other internal circuits. There is also a trend towards designing some portions of a single chip to run on multiple independent clocks to address the problem of clock skew across a relatively large chip surface area.
These and other considerations have increased the need for asynchronous clock domain crossing techniques. This need has been met in several different ways. One solution is to combine signals in the two domains into one signal that is common to both domains. However, this approach cannot always be accommodated easily.
Another approach uses a handshake mechanism to ensure proper synchronization. In this scheme, both the data and a control signal are sent from a sending clock domain to a receiving clock domain. After synchronizing the control signal, the receiver can then clock the data into a register. The control signal is then sent back to the sender as an acknowledgement. Once the acknowledgement is received, the sender can then send new data. With this approach, the sending clock domain and receiving clock domain must operate at approximately the same frequency for this scheme. Otherwise, latency problems ensue.
Another way to reliably pass information between clock domains is to use a First In First Out (FIFO) memory. In one arrangement, the FIFO can be a dual port memory having one port clocked by the sender and the other port clocked by the receiver. The advantage of using a FIFO is low-latency. But FIFOs tend to be more expensive and take up more room on a chip than other solutions.